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LH28F004SU-Z1 1 4m (512k 8) flash memory features ? 512k 8 word configuration ? 5 v write/erase operation (5 v v pp ) C no requirement for dc/dc converter to write/erase ? 100 ns maximum access time ? 32 independently lockable blocks (16k) ? 100,000 erase cycles per block ? automated byte write/block erase C command user interface C status register Cry ? /by ? status output ? system performance enhancement C erase suspend for read C two-byte write C full chip erase ? data protection C hardware erase/write lockout during power transitions C software erase/write lockout ? independently lockable for write/erase on each block (lock block and protect set/reset) ? 5 a (typ.) i cc in cmos standby ? 0.2 a (typ.) deep power-down ? state-of-the-art 0.55 m etox? flash technology ? 40-pin, 1.2 mm 10 mm 20 mm tsop (type i) package figure 1. tsop configuration 28f004sut-z1-1 top view 40-pin tsop 2 3 4 5 8 9 a 8 a 12 37 36 35 34 33 32 29 26 6 7 a 9 a 11 a 13 a 16 a 14 a 15 31 30 nc dq 6 10 11 12 39 38 nc 13 28 dq 3 dq 2 dq 1 27 dq 7 a 10 a 17 14 15 16 17 18 19 20 23 25 24 22 21 oe gnd ce a 0 a 3 a 2 a 4 a 1 a 7 a 6 a 18 a 5 gnd dq 5 dq 4 v cc v cc dq 0 40 1 v pp rp ry/by we nc
LH28F004SU-Z1 4m (512k 8) flash memory 2 figure 2. LH28F004SU-Z1 block diagram output buffer input buffer dq 0 - dq 7 id register output multiplexer csr esrs data comparator data queue register register i/o logic cui wsm 16kb block 0 16kb block 1 16kb block 30 16kb block 31 . . . . . . y gating/sensing y-decoder x-decoder oe ce we rp program/ erase voltage switch v pp v cc gnd ry/by address counter address queue latch input buffer a 0 - a 18 . . . 28f004sut-z1-2
4m (512k 8) flash memory LH28F004SU-Z1 3 symbol type name and function a 0 - a 13 input word-select addresses: select a word within one 16k block. these addresses are latched during data writes. a 14 - a 18 input block-select addresses: select 1 of 32 erase blocks. these addresses are latched during data writes, erase and lock-block operations. dq 0 - dq 7 input/output data input/output: inputs data and commands during cui write cycles. outputs array, buffer, identifier or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. ce ? input chip enable input: activate the devices control logic, input buffers, decoders and sense amplifiers. ce ? must be low to select the device. rp ? input reset/power-down: rp ? low places the device in a deep power-down state. all circuits that burn static power, even those circuits enabled in standby mode, are turned off. when returning from deep power-down, a recovery time of 550 ns is required to allow these circuits to power-up. when rp ? goes low, any current or pending wsm operation(s) are terminated, and the device is reset. all status registers return to ready (with all status flags cleared). oe ? input output enable: gates device data through the output buffers when low. the outputs float to tri-state off when oe ? is high. we input write enable: controls access to the cui, data queue registers and address queue latches. we is active low, and latches both address and data (command or array) on its rising edge. ry ? /by ? open drain output ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. when the wsm is ready for new operation or erase is suspended, or the device is in deep power-down mode ry ? /by ? pin is floated. v pp supply erase/write power supply (5.0 v 0.5 v): for erasing memory array blocks or writing words/bytes into the flash array. v cc supply device power supply (5.0 v 0.5 v): do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: no internal connection to die, lead may be driven or left floating pin description
LH28F004SU-Z1 4m (512k 8) flash memory 4 introduction sharps LH28F004SU-Z1 4m flash memory is a revo- lutionary architecture which enables the design of truly mobile, high performance, personal computing and com- munication products. with innovative capabilities, 5 v single voltage operation and very high read/write per- formance, the LH28F004SU-Z1 is also the ideal choice for designing embedded mass storage flash memory systems. the LH28F004SU-Z1 is a very high density, highest performance non-volatile read/write solution for solid- state storage applications. its independently lockable 32 symmetrical blocked architecture (16k each) extended cycling, low power operation, very fast write and read performance and selective block locking pro- vide a highly flexible memory component suitable for high density memory cards, resident flash arrays and pcmcia-ata flash drives. the LH28F004SU-Z1s single power supply operation enables the design of memory cards which can be read/written in 5.0 v sys- tems. its x8 architecture allows the optimization of memory to processor interface. the flexible block lock- ing option enables bundling of executable application software in a resident flash array or memory card. manufactured on sharps 0.55 m etox? process technology, the LH28F004SU-Z1 is the most cost- effective, high-density 5.0 v flash memory. description the LH28F004SU-Z1 is a high performance 4m (4,194,304 bit) block erasable non-volatile random access memory organized as 512k 8. the LH28F004SU-Z1 includes thirty-two 16k (16,384) blocks. a chip memory map is shown in figure 3. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use. among the significant enhancements of the LH28F004SU-Z1: ? 5 v read, write/erase operations (5 v v cc , v pp ) ? low power capability ? improved write performance ? dedicated block write/erase protection ? command-controlled memory protection set/reset capability the LH28F004SU-Z1 will be available in a 40-pin, 1.2 mm thick 10 mm 20 mm tsop (type i) pack- age. this form factor and pinout allow for very high board layout densities. a commander user interface (cui) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. internal algorithm automation allows byte wr ites and block erase operations to be executed using a two- write command sequence to the cui in the same way as the lh28f008sa 8m flash memory. a superset of commands have been added to the basic lh28f008sa command-set to achieve higher write performance and provide additional capabilities. these new commands and features include: ? software locking of memory blocks ? memory protection set/reset capability ? two-byte successive writes in 8-bit systems ? erase all unlocked blocks writing of memory data is performed typically within 13 s. a block erase operation erases one of the 32 blocks in typically 0.6 seconds, independent of the other blocks. LH28F004SU-Z1 allows to erase all unlocked blocks. it is desirable in case you have to implement erase op- eration maxmum 32 times. LH28F004SU-Z1 enab les tw o-byte ser ial write w hich is operated by three times command input. this feature can improve system write performance by up to typi- cally 10 s per byte. all operations are started by a sequence of write commands to the device. status register (described in detail later) and a ry ? /by ? output pin provide informa- tion on the progress of the requested operation. same as the lh28f008sa, LH28F004SU-Z1 requires an operation to complete before the next operation can be requested, also it allows to suspend block erase to read data from any other block, and al- low to resume erase operation. the LH28F004SU-Z1 provides user-selectable block locking to protect code or data such as device drivers, pcmcia card information, rom-executable os or application code. each block has an associated non- volatile lock-bit which determines the lock status of the block. in addition, the LH28F004SU-Z1 has a software controlled master write protect circuit which prevents any modifications to memory blocks whose lock-bits are set.
4m (512k 8) flash memory LH28F004SU-Z1 5 figure 3. memory map when the device power-up or rp ? turns high, write protect set/confirm command must be written. other- wise, all lock bits in the device remain being locked, cant perform the write to each block and single block erase. write protect set/confirm command must be written to reflect the actual lock status. however, when the device power-on or rp ? turns high, erase all un- locked blocks can be used. if used, erase is performed with reflecting actual lock status, and after that write and block erase can be used. the LH28F004SU-Z1 contains status register to accomplish various functions: ? a compatible status register (csr) which is 100% compatible with the lh28f008sa flash memorys status register. this register, when used alone, provides a straightforward upgrade capabil- ity to the LH28F004SU-Z1 from a lh28f008sa based design. the LH28F004SU-Z1 incorporates an open drain ry ? /by ? output pin. this feature allows the user to or- tie many ry ? /by ? pins together in a multiple memory con- figuration such as a resident flash array. the LH28F004SU-Z1 is specified for a maximum access time of 100 ns (t acc ) at 5 v operation (4.5 to 5.5 v) over the commercial temperature range (0 to +70c). the LH28F004SU-Z1 incorporates an automatic power saving (aps) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 2 ma at 5.0 v. a deep power-down mode of operation is invoked when the rp ? (called pwd on the lh28f008sa) pin transitions low. this mode brings the device power con- sumption to less than 5 a, and provides additional write protection by acting as a device reset pin during power transitions. a reset time of 550 ns is required from rp ? switching high until outputs are again valid. in the deep power-down state, the wsm is reset (any current operation will abort) and the csr register is cleared. a cmos standby mode of operation is enabled when ce ? transitions high and rp ? stays high with all input control pins at cmos levels. in this mode, the device draws an i cc standby current of 10 a. memory map 15 7c000h 7ffffh 7bfffh 78000h 77fffh 74000h 73fffh 70000h 6ffffh 6c000h 6bfffh 68000h 67fffh 64000h 63fffh 60000h 5ffffh 5c000h 5bfffh 58000h 57fffh 54000h 53fffh 50000h 4ffffh 4c000h 4bfffh 48000h 47fffh 44000h 43fffh 40000h 3ffffh 3c000h 3bfffh 38000h 37fffh 34000h 33fffh 30000h 2ffffh 2c000h 2bfffh 28000h 27fffh 24000h 23fffh 20000h 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 14 13 12 11 10 9 8 7 6 5 4 3 2 0 16kb block 16 16kb block 17 16kb block 18 16kb block 19 16kb block 20 16kb block 21 16kb block 22 16kb block 23 16kb block 24 16kb block 25 16kb block 26 16kb block 27 16kb block 28 16kb block 29 16kb block 30 16kb block 31 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 16kb block 1 16kb block 16kb block 28f004sut-z1-3
LH28F004SU-Z1 4m (512k 8) flash memory 6 bus operations, commands and status register definitions bus operations mode rp ? ce ? oe ? we a 0 dq 0-7 ry/by# note read v ih v il v il v ih xd out x1, 2, 7 output disable v ih v il v ih v ih x high-z x 1, 6, 7 standby v ih v ih x x x high-z x 1, 6, 7 deep power-down v il xxxxhigh-zv oh 1, 3 manufacturer id v ih v il v il v ih v il b0h v oh 4 device id v ih v il v il v ih v ih id v oh 4 write v ih v il v ih v il xd in x1, 5, 6 notes: 1. x can be v ih or v il for address or control pins except for ry ? /by ? , which is either v ol or v oh . 2. ry ? /by ? output is open drain. when the wsm is ready, erase is suspended or the device is in deep power-down mode, ry ? /by ? will be at v oh if it is tied to v cc through a resistor. when the ry ? /by ? at v ol is independent of oe ? while a wsm operation is in progress. 3. rp ? at gnd 0.2 v ensures the lowest deep power-down current. 4. a 0 at v il provide manufacturer id codes. a 0 at v ih provide device id codes. device id code = 21h. all other addresses are set to zero. 5. commands for different erase operations, d ata write oper ations, and lock-block operations can only be successfully completed when v pp = v pph . 6. while the wsm is running, ry ? /by ? in level-mode (default) stays at v ol until all operations are complete. ry ? /by ? goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry ? /by ? may be at v ol while the wsm is busy performing various operations. for example, a status register read during a write operation. 8. only to rp ? , v ih (min.) = 2.4 v at ttl-level input.
4m (512k 8) flash memory LH28F004SU-Z1 7 command first bus cycle second bus cycle note oper. address data oper. address data read array write x ffh read aa ad intelligent identifier write x 90h read ia id 1 read compatible status register write x 70h read x csrd 2 clear status register write x 50h 3 word write write x 40h write wa wd alternate word write write x 10h write wa wd block erase/confirm write x 20h write ba d0h 4 erase suspend/resume write x b0h write x d0h 4 lh28f008sa-compatible mode command bus definitions address data aa = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data wa = write address wd = write data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature codes. 2. the csr is automatically available after device enters data write, erase or suspend operations. 3. clears csr.3, csr.4, and csr.5. see status register definitions. 4. while device performs block erase, if you issue erase suspend command (b0h), be sure to confirm ess (erase-suspend-status) is set to 1 on compatible status register. in the case, ess bit was not set to 1, also completed the erase (ess = 0, wsms = 1), be sure to issue resume command (d0h) after completed next erase command. beside, when the erase suspend command is issued, while the device is not in erase, be sure to issue resume command (d0h) after the next erase complete. LH28F004SU-Z1 performance enhancement command bus definitions address data ba = block address ad = array data wa = write address wd (l, h) = write data (low, high) x = dont care wd (h, l) = write data (high, low) notes: 1. after initial device power-up, or return from deep power-down mode, the block lock status bit default to the locked state independent of the data in the corresponding lock bits. in order to upload the lock bit status, it requires to write protect set/confirm command. 2. to reflect the actual lock-bit status, the protect set/confirm command must be written after lock block/confirm command. 3. when protect reset/confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits. 4. the lock block/confirm command must be written after protect reset/confirm command was written. 5. a 10 is automatically complemented to load second byte of data a 10 value determines which wd is supplied first: a 10 = 0 looks at the wdl, a 10 = 1 looks at the wdh. 6. second bus cycle address of protect set/confirm and protect reset/confirm command is 0ffh. specifically a 9 - a 8 = 0, a 7 - a 0 = 1, others are dont care. command mode first bus cycle second bus cycle third bus cycle note oper. add. data oper. add. data oper. add. data protect set/confirm write x 57h write 0ffh d0h 1, 2 protect reset/confirm write x 47h write 0ffh d0h 3 lock block/confirm write x 77h write ba d0h 1, 2, 4 erase all unlocked blocks write x a7h write x d0h 1, 2 two-byte write x8 write x fbh write a10 wd (l, h) write wa wd (h, l) 1, 2, 5
LH28F004SU-Z1 4m (512k 8) flash memory 8 wsms ess es dws vpps r r r 76543210 compatible status register 4m flash memory software algorithms overview with the advanced command user interface, its per- formance enhancement commands and status regis- ters, the software code required to perform a given operation may become more intensive but it will result in much higher write/erase performance compared with current flash memory architectures. the software flowcharts describing how a given operation proceeds are shown here. figures 4 through 6 depict flowcharts using the 2nd generation flash de- vice in the lh28f008sa-compatible mode. figures 7 through 12 depict flowcharts using the 2nd generation flash devices performance enhancement commands mode. when the device power-up or the device is reset by rp ? pin, all blocks come up locked. therefore, word write, two byte ser ial wr ite and block erase can not csr.7 = write state machine status (wsms) 1 = ready 2 = busy csr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase csr.4 = data-write status (dws) 1 = error in data write 0 = data write successful csr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok notes: 1. ry ? /by ? output or wsms bit must be checked to determine completion of an operation (erase suspend, erase or data write) before the appropriate status bit (ess, es or dws) is checked for success. 2. if dws and es are set to 1 during an erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. 3. the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp s level only after the data-write or erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v ppl and v pph . 4. csr.2 - csr.0 = reserved for further enhancements. these bits are reserved for future use and should be masked out when polling the csr. be performed in each block. however, at that time, erase all unlocked block is performed normally, if used, and reflect actual lock status, also the unlocked block data is erased. when the device power-up or the device is reset by rp ? pin, set write protect command must be written to reflect actual block lock status. reset wr ite protect command must be written be- fore wr ite block lock command. to reflect actual block lock status, set write protect command is succeeded. reset write protect command enables write/erase operation to each block. in the case of block erase is performed, the block lock information is also erased. block lock command and set write protect command must be written to pro- hibit write/erase operation to each block. there are unassigned commands. it is not recom- mended that the customer use any command other than the valid commands specified in command bus defi- nitions. sharp reserved the right to redefine these codes for future functions.
4m (512k 8) flash memory LH28F004SU-Z1 9 figure 4. word/byte writes with compatible status register start bus operation command comments write 40h or 10h write data/address csr.7 = 0 1 0 1 0 1 csr full status check if desired operation complete clear csrd retry/error recovery data write successful v pp low detect read csrd (see above) csr.4, 5 = csr.3 = write write read standby word/byte write d = 40h or 10h a = x d = wd a = wa q = csrd toggle ce or oe to update csrd. a = x repeat for subsequent word/byte writes. csr full status check can be done after each word/byte write, or after a sequence of word/byte writes. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy bus operation command csr full status check procedure comments standby standby check csr.4, 5 1 = data write unsuccessful 0 = data write successful check csr.3 1 = v pp low detect 0 = v pp ok csr.3, 4, 5 should be cleared, if set, before further attempts are initiated. 28f004sut-z1-4 read compatible status register
LH28F004SU-Z1 4m (512k 8) flash memory 10 figure 5. block erase with compatible status register start bus operation command comments write 20h write d0h and block address csr.7 = 0 no yes 1 0 1 0 1 csr full status check if desired operation complete clear csrd retry/error recovery erase successful v pp low detect read csrd (see above) suspend erase suspend erase loop csr.4, 5 = csr.3 = write write read standby block erase confirm d = 20h a = x d = d0h a = ba q = csrd toggle ce or oe to update csrd a = x repeat for subsequent block erasures. csr full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy bus operation command csr full status check procedure comments standby standby check csr.4, 5 1 = erase error 0 = erase successful both 1 = command sequence error csr.3, 4, 5 should be cleared, if set, before further attempts are initiated. 28f004sut-z1-5 read compatible status register check csr.3 1 = v pp low detect 0 = v pp ok
4m (512k 8) flash memory LH28F004SU-Z1 11 figure 6. erase suspend to read array with compatible status register start bus operation command comments write b0h csr.7 = 0 1 0 1 read array data erase resumed erase completed write read standby erase suspend d = b0h a = x q = csrd toggle ce or oe to update csrd. a = x see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy standby check csr.6 1 = erase suspended 0 = erase completed write read array d = ffh a = x write erase resume d = d0h a = x read q = ad read must be from block other than the one suspended. 28f004sut-z1-6 write ffh write d0h read compatible status register csr.6 = done reading read array data write ffh no yes
LH28F004SU-Z1 4m (512k 8) flash memory 12 figure 7. block locking scheme start bus operation command comments csr.7 = 0 1 operation complete read read read write reset write protect q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy d = d0h a = ba q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy note: see csr full status check for data-write operation. if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. write ffh after the last operation to reset device to read array mode. see command bus definitions for description of codes. after write d = 47h a = x, write d = d0h a = 0ffh write lock block confirm set write protect d = 77h a = x after write d = 57h a = x, write d = d0h a = 0ffh write write 28f004sut-z1-7 read compatible status register reset wp read compatible status register write d0h and block address read compatible status register csr.7 = csr.7 = csr.4, 5 = 0 1 1 0 1 0 lock another block no yes (note) write 77h set wp
4m (512k 8) flash memory LH28F004SU-Z1 13 figure 8. updating data in a locked block start operation complete operation complete flow to add data notes: 1. use reset-write-protect flowchart. enable write/erase operation to all blocks. 2. use block-erase flowchart. erasing a block clears any previously established lockout for that block. 3. use set-write-protect flowchart. this step re-implements protection to locked blocks. 4. use word/byte-write or 2-byte-write flowchart sequences to write data. 5. use block-lock flowchart to write lock bit if desired. flow to rewrite data 28f004sut-z1-8 reset wp (note 1) erase block (note 2) set wp (note 3) start reset wp (note 1) write more data to block (note 4) set wp (note 3) write new data to block (note 4) relock block (note 5)
LH28F004SU-Z1 4m (512k 8) flash memory 14 figure 9. two-byte serial writes with compatible status registers (40-pin tsop) start bus operation command comments csr.7 = 0 1 operation complete read (apply to lh28f004su, x8, 40tsop) write write 2-byte write q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy d = wd a 10 = 0 loads low byte of data register. a 10 = 1 loads high byte of data register. other addresses = x note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. csr full status check can be done after each 2-byte write, or after a sequence of 2-byte writes. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = fbh a = x write d = wd a = wa internally, a 10 is automatically complemented to load the alternate byte location of the data register. read 28f004sut-z1-9 read compatible status register write fbh write data/a 10 csr.7 = csr.4, 5 = 1 0 1 0 another 2-byte write no yes (note) write data/address read compatible status register
4m (512k 8) flash memory LH28F004SU-Z1 15 figure 10. two-byte serial writes with compatible status registers (56-pin tsop, 44-pin sop) start bus operation command comments csr.7 = 0 1 operation complete read write write 2-byte write q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy q = csrd toggle ce or oe to update csrd. 1 = wsm ready 0 = wsm busy d = wd a -1 = 0 loads low byte of data register. a -1 = 1 loads high byte of data register. other addresses = x note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. csr full status check can be done after each 2-byte write, or after a sequence of 2-byte writes. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = fbh a = x write d = wd a = wa internally, a -1 is automatically complemented to load the alternate byte location of the data register. read 28f004sut-z1-10 read compatible status register write fbh write data/a -1 csr.7 = csr.4, 5 = 1 0 1 0 another 2-byte write no yes (note) write data/address read compatible status register (apply to lh28f400su, x16/8, 56tsop/44sop)
LH28F004SU-Z1 4m (512k 8) flash memory 16 figure 11. erase all unlocked blocks with compatible status registers start bus operation command comments write a7h csr.7 = 0 yes no 1 0 1 0 1 csr full status check if desired operation complete write d0h clear csrd retry/error recovery erase successful v pp low detect read csrd (see above) suspend erase suspend erase loop csr.4, 5 = csr.3 = write write read standby erase all unlocked blocks confirm d = a7h a = x d = d0h a = x q = csrd toggle ce or oe to update csrd a = x csr full status check can be done after erase all unlocked block, or after a sequence of erasures. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. check csr.7 1 = wsm ready 0 = wsm busy bus operation command csr full status check procedure comments standby standby check csr.4, 5 1 = erase error 0 = erase successful both 1 = command sequence error csr.3, 4, 5 should be cleared, if set, before further attempts are initiated. 28f004sut-z1-11 read compatible status register check sr.3 1 = v pp low detect 0 = v pp ok
4m (512k 8) flash memory LH28F004SU-Z1 17 figure 12. set write protect start csr.7 = 0 1 write 57h write confirm data/address read compatible status register csr.7 = 0 0 1 1 (note) csr.4, 5 = 28f004sut-z1-12 read compatible status register operation complete bus operation command comments read write write set write protect set confirm check csr.7 1 = wsm ready 0 = wsm busy d = d0h a = 0ffh (a 9 - a 8 = 0, a 7 - a 0 = 1, others = x) note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. upon device power-up or toggle rp, set write protect command must be written to reflect the actual lock-bit status. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = 57h a = x read check csr.7 1 = wsm ready 0 = wsm busy read check csr.4, 5 1 = unsuccesful 0 = successful
LH28F004SU-Z1 4m (512k 8) flash memory 18 figure 13. reset write protect start csr.7 = 0 1 write 47h write confirm data/address read compatible status register csr.7 = 0 0 1 1 (note) csr.4, 5 = 28f004sut-z1-13 read compatible status register operation complete bus operation command comments read write write reset write protect reset confirm check csr.7 1 = wsm ready 0 = wsm busy d = d0h a = 0ffh (a 9 - a 8 = 0, a 7 - a 0 = 1, others = x) note: if csr.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. reset write protect command enables write/erase operation to all blocks. write ffh after the last operation to reset device to read array mode. see command bus cycle notes for description of codes. d = 47h a = x read check csr.7 1 = wsm ready 0 = wsm busy read check csr.4, 5 1 = unsuccesful 0 = successful
4m (512k 8) flash memory LH28F004SU-Z1 19 * warning: stressing the device bey ond the abso- lute maximum ratings may cause permanent dam- age. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the oper ating conditions may affect device reliability. electrical specifications absolute maximum ratings* temperature under bias ......................... 0c to +80c storage temperature ......................... -65c to +125c v cc = 5.0 v 0.5 v systems 4 symbol parameter min. max. units test conditions note t a operating temperature, commercial 0 70.0 c ambient temperature 1 v cc v cc with respect to gnd -0.2 7.0 v 2 v pp v pp supply voltage with respect to gnd -0.2 7.0 v 2 v voltage on any pin (except v cc , v pp ) with respect to gnd -0.5 7.0 v 2 i current into any non-supply pin 30 ma i out output short circuit current 100.0 ma 3 notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is -0.5 v on input/output pins. during transitions, this level may undershoot to -2.0 v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5 v which, during transitions, may overshoot to v cc + 2.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. ac specifications are valid at both voltage ranges. see dc characteristics tables for voltage range-specific specifications. capacitance for 5.0 v systems symbol parameter typ. max. units test conditions note c in capacitance looking into an address/control pin 710pft a = 25c, f = 1.0 mhz 1 capacitance looking into an address/control pin a 10 912pft a = 25c, f = 1.0 mhz 1 c out capacitance looking into an output pin 9 12 pf t a = 25c, f = 1.0 mhz 1 c load load capacitance driven by outputs for timing specifications 100 pf for v cc = 5.0 v 0.5 v 1 equivalent testing load circuit v cc 10% 2.5 ns 25 w transmission line delay note: 1. sampled, not 100% tested.
LH28F004SU-Z1 4m (512k 8) flash memory 20 timing nomenclature for 5.0 v systems use the standard jedec cross point definitions. each timing parameter consists of 5 characters. some common examples are defined below: t ce t elqv time (t) from ce ? (e) going low (l) to the outputs (q) becoming valid (v) t oe t glqv time (t) from oe ? (g) going low (l) to the outputs (q) becoming valid (v) t acc t avqv time (t) from address (a) valid (v) to the outputs (q) becoming valid (v) t as t avwh time (t) from address (a) valid (v) to we ? (w) going high (h) t dh t whdx time (t) from we ? (w) going high (h) to when the data (d) can become undefined (x) figure 14. transient input/output reference waveform (v cc = 5.0 v) figure 15. transient equivalent testing load circuit (v cc = 5.0 v) pin characters pin states a address inputs h high d data inputs l low q data outputs v valid ece ? (chip enable) x driven, but not necessarily valid goe ? (output enable) z high impedance w we (write enable) prp ? (deep power-down pin) rry ? /by ? (ready/busy) v any voltage level 5 v v cc at 4.5 v min. input test points output 2.4 0.45 2.0 0.8 2.0 0.8 28f004sut-z1-14 note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic '1' and v ol (0.45 v ttl ) for a logic '0'. input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. 2.5 ns of 25 w transmission line total capacitance = 100 pf from output under test test point 28f004sut-z1-15
4m (512k 8) flash memory LH28F004SU-Z1 21 dc characteristics v cc = 5.0 v 0.5 v, t a = 0c to +70c symbol parameter typ. min. max. units test conditions note i il input load current 1 a v cc = v cc max., v in = v cc or gnd 1 i lo output leakage current 10 a v cc = v cc max., v in = v cc or gnd 1 i ccs v cc standby current 510a v cc = v cc max., ce ? , rp ? = v cc 0.2 v 1,4 14ma v cc = v cc max., ce ? , rp ? = v ih i ccd v cc deep power-down current 0.2 5 a rp ? = gnd 0.2 v 1 i ccr 1 v cc read current 60 ma v cc = v cc max., cmos: ce ? = gnd 0.2 v inputs = gnd 0.2 v or v cc 0.2 v ttl: ce ? = v il inputs = v il or v ih f = 10 mhz, i out = 0 ma 1, 3, 4 i ccr 2 v cc read current 13 30 ma v cc = v cc max., cmos: ce ? = gnd 0.2 v inputs = gnd 0.2 v or v cc 0.2 v ttl: ce ? = v il inputs = v il or v ih f = 5 mhz, i out = 0 ma 1, 3, 4 i ccw v cc write current 18 35 ma byte/two-byte serial write in progress 1 i cce v cc block erase current 18 25 ma block erase in progress 1 i cces v cc erase suspend current 510ma ce ? = v ih block erase suspended 1, 2 i pps v cc standby current 10 a v pp v cc 1 i ppd v pp deep power-down current 0.2 5 a rp ? = gnd 0.2 v 1
LH28F004SU-Z1 4m (512k 8) flash memory 22 dc characteristics (continued) v cc = 5.0 v 0.5 v, t a = 0c to +70c notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0 v, v pp = 5.0 v, t = 25c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. automatic power saving (aps) reduces i ccr to less than 2 ma in static operation. 4. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 5. only to rp ? , v ih (min.) = 2.4 v at ttl-level input. symbol parameter type min. max. units test conditions note i ppr v pp read current 65 200 a v pp > v cc 1 i ppw v pp write current 15 35 ma v pp = v pph , byte/two-byte serial write in progress 1 i ppe v pp erase current 20 40 ma v pp = v pph , block erase in progress 1 i ppes v pp erase suspend current 65 200 a v pp = v pph , block erase suspended 1 v il input low voltage -0.5 0.8 v 5 v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage 0.45 v v cc = v cc min. and i ol = 5.8 ma v oh 1 output high voltage 0.85 v cc v i ol = -2.5 ma v cc = v cc min. v oh 2 v cc - 0.4 v i ol = -100 a v cc = v cc min. v ppl v pp during normal operations 0.0 5.5 v v pph v pp during write/erase operations 5.0 4.5 5.5 v v lko v cc erase/write lock voltage 1.4 v
4m (512k 8) flash memory LH28F004SU-Z1 23 ac characteristics - read only operations 1 v cc = 5.0 v 0.5 v, t a = 0c to +70c symbol parameter min. max. units note t avav read cycle time 100 ns t avgl address setup to oe ? going low 0 ns 3 t avqv address to output delay 100 ns t elqv ce ? to output delay 100 ns 2 t phqv rp ? high to output delay 550 ns 4 t glqv oe ? to output delay 40 ns 2 t elqx ce ? to output in low z 0 ns 3 t ehqz ce ? to output in high z 35 ns 3 t glqx oe ? to output in low z 0 ns 3 t ghqz oe ? to output in high z 35 ns 3 t oh output hold from address, ce ? or oe ? change, whichever occurs first 0ns3 notes: 1. see ac input/output reference waveforms for timing measurements, figure 4. 2. oe ? may be delayed up to t elqv - t glqv after the failing edge of ce ? without impact on t elqv . 3. sampled, not 100% tested. 4. only to rp ? , v ih (min.) = 2.4 v.
LH28F004SU-Z1 4m (512k 8) flash memory 24 figure 16. read timing waveforms 28f004sut-z1-16 t avav addresses stable v cc power-up standby device and address selection outputs enabled data valid standby v cc power-down addresses (a) v ih v il ce (e) v ih v il t avgl t glqv t elqv t glqx t elqx t avqv t phqv t ehqz t ghqz t oh oe (g) v ih v il we (w) v ih v il data (d/q) v oh v ol v cc 5.0 v gnd rp (p) v ih v il high-z high-z valid output . . . . . . . . . . . . . . . . . . . . .
4m (512k 8) flash memory LH28F004SU-Z1 25 power-up and reset timings figure 17. v cc power-up and rp ? reset waveforms symbol parameter min. max. units note t pl5v rp# low to v cc at 4.5 v min. 0 s 1 t avqv address valid to data valid for v cc 5 v 10% 100 ns 2 t phqv rp# high to data valid for v cc 5 v 10% 550 ns 2 notes: ce ? and oe ? are switched low after power-up. 1. the power supply may start to switch concurrently with rp ? going low. 2. the address access time and rp ? high to data valid time are shown for 5 v v cc operation. refer to the ac characteristics read only operations also. 28f004sut-z1-17 address (a) rp (p) data (q) t pl5v v cc (5 v) valid valid 5.0 v outputs 4.5 v 5.0 v t phqv t avqv v cc power up 0 v
LH28F004SU-Z1 4m (512k 8) flash memory 26 ac characteristics for we ? - controlled command write operations 1 v cc = 5.0 v 0.5 v, t a = 0c to +70c notes: 1. read timing during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. write/erase durations are measured to valid status register (csr) data. 5. byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we ? for all command write operations. symbol parameter typ. min. max. units note t avav write cycle time 100 ns t vpwh v pp set up to we going high 100 ns 3 t phel rp ? setup to ce ? going low 480 ns t elwl ce ? setup to we going low 0 ns t avwh address setup to we going high 60 ns 2, 6 t dvwh data setup to we going high 60 ns 2, 6 t wlwh we pulse width 60 ns t whdx data hold from we high 0 ns 2 t whax address hold from we high 10 ns 2 t wheh ce ? hold from we high 10 ns t whwl we pulse width high 50 ns t ghwl read recovery before write 0 ns t whrl we high to ry ? /by ? going low 100 ns t rhpl rp ? hold from valid status register data and ry ? /by ? high 0ns3 t phwl rp ? high recovery to we going low 1 s t whgl write recovery before read 80 ns t qvvl v pp hold from valid status register data and ry ? /by ? high 0s t whqv 1 duration of byte write operation 13 4.5 s 4, 5 t whqv 2 duration of block erase operation 0.3 s 4
4m (512k 8) flash memory LH28F004SU-Z1 27 figure 18. ac waveforms for command write operations addresses (a) (note 1) v ih v il a in v ih v il a in d in d in d in d in d out ce (e) v ih v il oe (g) v ih v il we (w) v ih v il data (d/q) v ih v il ry/by (r) v oh v ol rp (p) v ih v il t avav t avav t whgl t whwl t wlwh t dvwh t phwl t rhpl t qwl addresses (a) (note 2) t avwh t whax t avwh t whax t elwl t wheh t whqv 1, 2 t ghwl t whdx t whrl (note 4) t vpwh 28f004sut-z1-18 (note 3) high-z write data-write or erase setup command deep power-down write valid address and data (data-write) or erase confirm command automated data-write or erase delay notes: 1. this address string depicts data-write/erase cycles with corresponding verification via esrd. 2. this address string depicts data-write/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data-write/erase operations. 4. rp low transition is only to show t rhpl ; not valid for above read and write cycles. v pp (v) v pph v ppl read compatible status register data
LH28F004SU-Z1 4m (512k 8) flash memory 28 ac characteristics for ce ? - controlled command write operations 1 v cc = 5.0 v 0.5 v, t a = 0c to +70c notes: 1. read timing during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. write/erase durations are measured to valid status register (csr) data. 5. byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of ce ? for all command write operations. symbol parameter typ. min. max. units note t avav write cycle time 100 ns t phwl rp ? setup to we going low 480 ns 3 t vpeh v pp setup to ce ? going high 100 ns 3 t wlel we setup to ce ? going low 0 ns t aveh address setup to ce ? going high 60 ns 2, 6 t dveh data setup to ce ? going high 60 ns 2, 6 t eleh ce ? pulse width 60 ns t ehdx data hold from ce ? high 0 ns 2 t ehax address hold from ce ? high 10 ns 2 t ehwh we hold from ce ? high 10 ns t ehel ce ? pulse width high 50 ns t ghel read recovery before write 0 ns t ehrl ce ? high to ry ? /by ? going low 100 ns t rhpl rp ? hold from valid status register data and ry ? /by ? high 0ns3 t phel rp ? high recovery to ce ? going low 1 s t ehgl write recovery before read 80 ns t qvvl v pp hold from valid status register data and ry/by# high 0s t ehqv 1 duration of byte write operation 13 4.5 s 4, 5 t ehqv 2 duration of block erase operation 0.3 s 4
4m (512k 8) flash memory LH28F004SU-Z1 29 figure 19. alternate ac waveforms for command write operations addresses (a) (note 1) v ih v il a in v ih v il a in d in d in d in d in d out ce (e) v ih v il oe (g) v ih v il we (w) v ih v il data (d/q) v ih v il ry/by (r) v oh v ol rp (p) v ih v il t avav t avav t ehgl t ehel t eleh t dveh t phel t rhpl t qwl addresses (a) (note 2) t aveh t ehax t aveh t ehax t wlel t ehwh t ehqv 1, 2 t ghel t ehdx t ehrl (note 4) t vpeh 28f004sut-z1-19 (note 3) high-z write data-write or erase setup command deep power-down write valid address and data (data-write) or erase confirm command automated data-write or erase delay notes: 1. this address string depicts data-write/erase cycles with corresponding verification via esrd. 2. this address string depicts data-write/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data-write/erase operations. 4. rp low transition is only to show t rhpl ; not valid for above read and write cycles. v pp (v) v pph v ppl read compatible status register data
LH28F004SU-Z1 4m (512k 8) flash memory 30 erase and byte write performance v cc = 5.0 v 0.5 v, t a = 0c to +70c notes: 1. 25c, v pp = 5.0 v 2. excludes system-level overhead. 3. depends on the number of protected blocks. symbol parameter typ. (1) min. max. units test conditions note t whrh 1 byte write time 13 s 2 t whrh 2 two-byte serial write time 20 s 2 t whrh 3 16kb block write time 0.22 1.0 s byte write mode 2 t whrh 4 16kb block write time 0.17 1.0 s two-byte serial write mode 2 block erase time (16kb) 0.6 10 s 2 full chip erase time 8.8 - 14.4 s 2, 3
4m (512k 8) flash memory LH28F004SU-Z1 31 ordering information dimensions in mm [inches] maximum limit minimum limit 40tsop (tsop040-p-1020) 40tsop detail see detail 1.19 [0.047] max. 0 - 10? 0.22 [0.009] 0.02 [0.001] 1.10 [0.043] 0.90 [0.035] 0.49 [0.019] 0.39 [0.015] 0.49 [0.019] 0.39 [0.015] 0.125 [0.005] 10.20 [0.402] 9.80 [0.386] 0.50 [0.020] typ. 0.25 [0.010] 0.15 [0.006] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] 0.18 [0.007] 0.08 [0.003] 1 20 21 40 40-pin, 1.2 x 10 x 20 mm tsop (type i) (tsop040-p-1020) lh28f004su device type t package 28f004sut-z1-20 example: lh28f004sut-z1 (4m (512k x 8) flash memory, 100 ns, 40-pin tsop) 4m (512k x 8) flash memory -z1 speed 100 access time (ns)
sharp reserves the right to make changes in specifications at any time and without notice. sharp does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. north america europe asia sharp electronics corporation microelectronics group 5700 nw pacific rim blvd., m/s 20 camas, wa 98607, u.s.a. phone: (360) 834-2500 telex: 49608472 (sharpcam) facsimile: (360) 834-8903 http://www.sharpmeg.com sharp electronics (europe) gmbh microelectronics division sonninstra? 3 20097 hamburg, germany phone: (49) 40 2376-2286 telex: 2161867 (heeg d) facsimile: (49) 40 2376-2232 life support policy sharp components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the sharp corporation. sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: (07436) 5-1321 telex: labometa-b j63428 facsimile: (07436) 5-1532 warranty sharp warrants to customer that the products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. customer's exclusive remedy for breach of this warranty is that sharp will either (i) repair or replace, at its option, any product which fails during the warranty period because of such defect (if customer promptly reported the failure to sharp in writing) or, (ii) if sharp is unable to repair or replace, sharp will refund the purchase price of the product upon its return to sharp . this warranty does not apply to any product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than sharp . the warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. all express and implied warranties of merchantability, fitness for use and fitness for a particular purpose are specifically excluded. ? ?1997 by sharp corporation reference code smt96109 issued july 1995 LH28F004SU-Z1 4m (512k 8) flash memory

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